| |
| |
| Latch-Up Testing |
| |
The latch-up test is a special test used with CMOS processes to detect a state in which a low-impedance path, resulting from an overstress that triggers a parasitic thyristor structure, persists after removal or cessation of the triggering condition. STS uses JEDEC-JC-78 standard.The current is applied to each I/O pin in steps while the power supply current is monitored. The current into the test pin must rise to a minimum of 100 mA without latch-up occurring.
The following industry standards are used to test device for Latch-up test.
Latch-up
- EIA/JEDEC JESD78
- AEC-Q100-004-Rev C
|
