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Latch-up Testing
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Electro-Thermally Induced Parasitic Gate Leakage test
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Oryx EX 1100.2016 pin Tester
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Please help us understand the scope of work better by filling out the ESD and Latch-up request forms
Contact Name:
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Email:
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Company:
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Phone:
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Fax:
Address:
City:
State:
Country:
Website:
Please Provide Option To Upload Data From Personal Computer
Temperature at which devices should be tested:
Room Ambient and/or Maximum operating Temperature of
°C.
Please Specify Voltage & Current For Your Power Groups
PWR 1
Current
MA
Voltage
V
PWR 2
Current
MA
Voltage
V
PWR 3
Current
MA
Voltage
V
PWR 4
Current
MA
Voltage
V
PWR 5
Current
MA
Voltage
V
PWR 6
Current
MA
Voltage
V
Positive/Negative Current Latch-Up, Current Stress
Voltage to which device should be powered
V (Vddq)
Please provide a list of input pins with the state they should be set to (High or Low):
Device require preconditioning? (eg; after power-up)
Yes
No
If Yes, please describe in detail how the preconditioning should be performed
Trigger Current
A. Discrete level
mA (JEDEC 78A requires +/- 100mA)
B. Increment stress
Start
mA
Stop
mA
Step
mA
Over Voltage Supply Stress
Yes
No
A. Vstress= 1.5 Vmax (per JEDEC 78A)
B. Increment stress
Start
V
Stop
V
Step
V
Additional Information:
Security Code:
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